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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICR_IGROUPR0, Interrupt Group Register 0</h1><p>The GICR_IGROUPR0 characteristics are:</p><h2>Purpose</h2>
        <p>Controls whether the corresponding SGI or PPI is in Group 0 or Group 1.</p>
      <h2>Configuration</h2>
        <p>This register is available in all GIC configurations. If the GIC implementation supports two Security states, this register is Secure.</p>

      
        <p>A copy of this register is provided for each Redistributor.</p>
      <h2>Attributes</h2>
        <p>GICR_IGROUPR0 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit31</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit30</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit29</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit28</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit27</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit26</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit25</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit24</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit23</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit22</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit21</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit20</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit19</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit18</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit17</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit16</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit15</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit14</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit13</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit12</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit11</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit10</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit9</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit8</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit7</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit6</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit5</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit4</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit3</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Redistributor_group_status_bit0</a></td></tr></tbody></table><h4 id="fieldset_0-31_0">Redistributor_group_status_bit&lt;x&gt;, bit [x], for x = 31 to 0</h4><div class="field"><p>Group status bit. In this register:</p>
<ul>
<li>Bits [31:16] are group status bits for PPIs.
</li><li>Bits [15:0] are group status bits for SGIs.
</li></ul><table class="valuetable"><tr><th>Redistributor_group_status_bit&lt;x&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>When <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS==1, the corresponding interrupt is Group 0.</p>
<p>When <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS==0, the corresponding interrupt is Secure.</p></td></tr><tr><td class="bitfield">0b1</td><td><p>When <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS==1, the corresponding interrupt is Group 1.</p>
<p>When <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS==0, the corresponding interrupt is Non-secure Group 1.</p></td></tr></table>
      <p>When <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS == 0, the bit that corresponds to the interrupt is concatenated with the equivalent bit in <a href="ext-gicr_igrpmodr0.html">GICR_IGRPMODR0</a> to form a 2-bit field that defines an interrupt group. The encoding of this field is at <a href="ext-gicr_igrpmodr0.html">GICR_IGRPMODR0</a>.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a GIC reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><div class="text_after_fields">
    <p>The considerations for the reset value of this register are the same as those for <a href="ext-gicd_igrouprn.html">GICD_IGROUPR&lt;n&gt;</a> with n=0.</p>
  </div><h2>Accessing GICR_IGROUPR0</h2>
        <p>When affinity routing is not enabled for the Security state of an interrupt in GICR_IGROUPR0, the corresponding bit is <span class="arm-defined-word">RES0</span> and equivalent functionality is provided by <a href="ext-gicd_igrouprn.html">GICD_IGROUPR&lt;n&gt;</a> with n=0.</p>

      
        <p>When <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS == 0, the register is RAZ/WI to Non-secure accesses.</p>

      
        <p>Bits corresponding to unimplemented interrupts are RAZ/WI.</p>

      
        <div class="note"><span class="note-header">Note</span><p>Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.</p></div>
      <h4>GICR_IGROUPR0 can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Redistributor</td><td>SGI_base</td><td><span class="hexnumber">0x0080</span></td><td>GICR_IGROUPR0</td></tr></table><p>Accesses on this interface are <span class="access_level">RW</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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